The xDSL line cards go into slots 1 through 24 of an LCS backplane. Each card can serve a maximum of 8 lines — pretty poor compared to competing DSLAMs which typically support 24 lines per card. I defer to Nokia's own documentation for the description of how the line card outputs are wired to the LCS backplane.
It appears that the oldest line cards were those for ADSL/CAP: CAP2 and CAP4. (It's hard to believe that someone had made a full-sized line card that serves only 2 lines, but that appears to be the case indeed.) Then came various DMT4 and DMT8 variants (having very little interest in ADSL/DMT, I haven't really looked into those) and the SDSL/IDSL cards of interest to our Open WAN Connectivity Project. DS1 and G.shdsl (SHDSL8) line cards are the late comers to the party.
It appears that the earliest CAP2 line card used a 68360 processor
(supported by VXS36025 and portss.o code images
perhaps?), but all later line cards from CAP4 onward use PowerPC processors,
as evidenced by the respective *.o modules being PowerPC ELF
binaries.
This line card is special in that instead of switching ATM cells to its subscribers, it terminates AAL5 in an on-board SAR, does FRF.8 or other Layer 2 conversion from ATM to HDLC, and serves HDLC to the IDSL subscribers. The card consists of 8 MC145572 ISDN U interface transceivers, an MPC860SR processor and an Altera EPF10K10ATC144 FPGA. (This FPGA is the smallest of all D50 cards we've seen.)
The use of a PowerQUICC processor with ATM SAR support (the SR suffix) makes total sense given this card's function, but note that they've used MPC860SR rather than the cheaper MPC850SR. I have a suspicion that the 860 feature they needed which is missing in the 850 is support for two TDM bus interfaces. (The MPC850 family has just one.) The HDLC interface to the MC145572s must be QMC (there aren't enough SCCs to devote one to each IDSL circuit), and that requires TDM, so that's one TDM bus interface. My guess is that the other TDM bus interface was needed for the internal management network.
Of course IDSL is quite slow with its maximum date rate of 144 kbps, and this slowness must have been a significant factor in the design of this line card: IDSL8 is the only card among classic D50 ones on which the data path passes through the CPU instead of living entirely in FPGAs.
SDSL8 is the canonical Nokia SDSL line card. It uses Bt8970 bitpumps, hence 1.5 Mbps maximum and external hardware for switching data rates. The data rates implemented on the SDSL8 line card are 192, 384, 768, 1152 and 1536 kbps.
Aside from the 8 Bt8970 bitpumps, the card features an MPC850DE processor
and a big EPF10K50V FPGA.
The use of an MPC8xx processor is consistent with other xDSL line cards of
that era; MPC850DE is a nothing special
MPC8xx variant.
It has to manage startup on all 8 bitpumps (potentially CPU-intensive), but
it clearly stays out of the data path.
The EPF10K50V FPGA is clearly where the entire data path resides: interface to the ATM channel from the LSM, multiplexing between the 8 ports, and the weird framing format put into the SDSL bit stream.
I have never seen one of these cards with my own eyes, only read about it in Nokia's manuals and examined the D50 firmware suite to see how it's supported. Needless to say, we would love to get one of these cards for examination and experimentation, but we don't even know if they've ever been common or if they exist only in the form of unobtainium vapours.
SDSL8+ differs from the plain SDSL8 in that it supports the 2.3 Mbps data rate, obviously by way of using RS8973 bitpumps instead of Bt8970. RS8973 supports data rates from 144 to 2320 kbps in 8 kbps increments with internal clock generation and switching, and Nokia's documentation claims that all of these intermediate rates are supported at the high level as well.
Examination of the firmware bits tells us that:
sdsl8.o module, provided
that it's a new enough version.
sdsl8.rbf and
sdsl8p.rbf.
The latter RBF is bigger, so it's a different FPGA part or multiple FPGAs,
not just different logic inside.