The SK70704/SK70706 chipset from Level One (datasheet here) is a good example of a typical non-Brooktree HDSL chipset. Unlike Brooktree's bitpump this chipset can only be used for HDSL but not for SDSL. Contrasting the two chipsets gives one a good insight into how SDSL/2B1Q differs from HDSL and how Brooktree's chip played a pivotal role in it coming into being.

In terms of integration and self-sufficiency the Level One chipset feels closer to MC145572 than to Brooktree's bitpumps. No external microprocessor babysitting is needed; the activation state machine is implemented internally and is not tweakable. In terms of functionality the data pump works at a slightly higher level than a pure bit pump: rather than pass raw uninterpreted quats, the chipset implements the lowest-level functionality of an HDSL framer (sync word delineation and selective scrambling of the rest of the frame) and presents an interface in which 6 ms frames are delineated, the sync word is inserted by the data pump, but further bit meaning is assigned by the user. The internally implemented ASM relies on the HDSL frame sync word exactly as prescribed in HDSL standards (but not in SDSL/2B1Q).

This Level One chipset could not be used instead of the Brooktree bitpump in an SDSL/2B1Q implementation because:

• There is no way to make the data rate anything other than 784 kbps.
• The internally implemented ASM and selective scrambler require the HDSL 6 ms frame structure.

The only exception is the hypothetical SDSL Flavor H, but then we don't know if anyone has ever actually implemented such. It is interesting to ponder though what the SDSL world would have been like if a chip like SK70706 had been chosen instead of BT by the first pioneers — maybe then HDSL-style framing would have been the norm rather than the unframed flavors.